7831

Parallelization Strategies of the Canny Edge Detector for Multi-core CPUs and Many-core GPUs

Taieb Lamine Ben Cheikh, Giovanni Beltrame, Gabriela Nicolescu, Farida Cheriet, Sofiene Tahar
Department of Computer Science, Ecole Polytechnique de Montreal, Montreal, Canada
IEEE Northeast Workshop on Circuits and Systems (NEWCAS’12), 2012

@article{cheikh2012parallelization,

   title={Parallelization Strategies of the Canny Edge Detector for Multi-core CPUs and Many-core GPUs},

   author={Cheikh, T.L.B. and Beltrame, G. and Nicolescu, G. and Cheriet, F. and Tahar, S.},

   year={2012}

}

Download Download (PDF)   View View   Source Source   

866

views

In this paper we study two parallelization strategies (loop-level parallelism and domain decomposition), and we investigate their impact in terms of performance and scalability on two different parallel architectures. As a test application, we use the Canny Edge Detector due to its wide range of parallelization opportunities, and its frequent use in computer vision applications. Different parallel implementations of the Canny Edge Detector are run on two distinct hardware platforms, namely a multi-core CPU, and a many-core GPU. Our experiments uncover design rules that, depending on a set of applications and platform factors (parallel features, data size, and architecture), indicate which parallelization scheme is more suitable.
No votes yet.
Please wait...

* * *

* * *

HGPU group © 2010-2017 hgpu.org

All rights belong to the respective authors

Contact us: