The 19th IEEE International Symposium on High Performance Computer Architecture Collocated with PPoPP-2013 and CGO-2013, HPCA-2013
The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to:
* Processor, cache, and memory architectures
* Parallel computer architectures
* Multicore architectures
* Impact of technology on architecture
* Power-efficient architectures and techniques
* Dependable/secure architectures
* High-performance I/O systems
* Embedded and reconfigurable architectures
* Interconnect and network interface architectures
* Architectures for cloud-based HPC
* Innovative hardware/software trade-offs
* Impact of compilers and system software on architecture
* Performance modeling and evaluation
* Architectures for emerging technology and applications
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Most viewed papers (last 30 days)
- Graphics Programming on the Web WebCL Course Notes
- Use NVIDIA CUDA technology to create genetic algorithms with extensive population
- Simulating the universe with GPU-accelerated supercomputers: n-body methods, tests, and examples
- Secrets from the GPU
- Implementations of the FFT algorithm on GPU
- GPU Scripting and Code Generation with PyCUDA
- Fluid Motion Modelling Using Vortex Particle Method on GPU
- One OpenCL to Rule Them All?
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Rating
Duality based optical flow algorithms with applications
Adaptive Dynamic Load Balancing in Heterogeneous Multiple GPUs-CPUs Distributed Setting: Case Study of B&B Tree Search
Graphics Programming on the Web WebCL Course Notes
OpenCL parallel Processing using General Purpose Graphical Processing units - TiViPE software development
Comprehensive Analysis of High-Performance Computing Methods for Filtered Back-Projection
Optimizing MapReduce for GPUs with effective shared memory usage
A parallel decoding algorithm of LDPC codes using CUDA
Kernelet: High-Throughput GPU Kernel Executions with Dynamic Slicing and Scheduling
CUDA implementation of the algorithm for simulating the epidemic spreading over large networks
Stencil-Aware GPU Optimization of Iterative Solvers
Recent source codes
Events
October 1-4, 2013 Lyon, France The 2013 International Workshop on Embedded Multicore Systems, ICPP-EMS 2013 |
November 13-15, 2013 Zhangjiajie, China 3rd International Workshop on Embedded Multi-core Computing and Applications, EMCA 2013 |
February 2-6, 2014 San Francisco, USA |
February 12-14, 2014 Turin, Italy |
November 11-14, 2013 San Jose, California, USA |
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