8062

Dynamic Warp Resizing in High-Performance SIMT

Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari
School of ECE, University of Tehran
arXiv:1208.2374v1 [cs.AR] (11 Aug 2012)

@article{2012arXiv1208.2374L,

   author={Lashgar, Ahmad and Baniasadi, Amirali and Khonsari, Ahmad},

   title={"{Dynamic Warp Resizing in High-Performance SIMT}"},

   journal={ArXiv e-prints},

   archivePrefix={"arXiv"},

   eprint={1208.2374},

   primaryClass={"cs.AR"},

   keywords={Hardware Architecture},

   year={2012},

   month={aug}

}

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Modern GPUs synchronize threads grouped in a warp at every instruction. These results in improving SIMD efficiency and makes sharing fetch and decode resources possible. The number of threads included in each warp (or warp size) affects divergence, synchronization overhead and the efficiency of memory access coalescing. Small warps reduce the performance penalty associated with branch and memory divergence at the expense of a reduction in memory coalescing. Large warps enhance memory coalescing significantly but also increase branch and memory divergence. Dynamic workload behavior, including branch/memory divergence and coalescing, is an important factor in determining the warp size returning best performance. Optimal warp size can vary from one workload to another or from one program phase to the next. Based on this observation, we propose Dynamic Warp Resizing (DWR). DWR takes innovative microarchitectural steps to adjust warp size during runtime and according to program characteristics. DWR outperforms static warp size decisions, up to 1.7X to 2.28X, while imposing less than 1% area overhead. We investigate various alternative configurations and show that DWR performs better for narrower SIMD and larger caches.
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