Scan Test Power Simulation on GPGPUs

S. Holst, E. Schneider, H.-J. Wunderlich
University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
IEEE 21st Asian Test Symposium (ATS), 2012

   title={Scan Test Power Simulation on GPGPUs},

   author={Holst, S. and Schneider, E. and Wunderlich, H.J.},

   booktitle={Test Symposium (ATS), 2012 IEEE 21st Asian},





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The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.
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