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Implementing an architecture for efficient network traffic processing on modern graphics hardware

Lazaros Koromilas
Computer Science Department, School of Sciences and Engineering, University of Crete
University of Crete, 2012
@article{koromilas2012implementing,

   title={Implementing an architecture for efficient network traffic processing on modern graphics hardware},

   author={Koromilas, Lazaros},

   year={2012}

}

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Network traffic processing is necessary in order to develop active components in the infrastructure of the network, such as routers, or passive applications, such as network intrusion detection systems. However, in today’s high-speed network links this has become a very challenging task in terms of computational resources. Custom hardware appliances that can handle high packet rates are rather expensive and offer limited programmability. This work presents the design and implementation of a high-performance software packet processing system using high-speed network interfaces, multi-core processors and many-core graphics hardware. The massive parallelism of modern graphics chips is exploited for efficient packet processing, which effectively frees cycles on the main processor. The development of the system focuses on high-throughput data movement techniques, memory access optimizations, domain specific data structures and the configuration of a large set of parameters that enables high processing rates. The evaluation of the system has shown that it can passively process real-world traffic at 18 Gbps, with latency in the order of few milliseconds. In active mode, where packets are forwarded, the system can achieve a 13.5 Gbps rate. There is an up to 15 times increase in throughput when compared to traditional approaches.
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