Advanced Video Coding on CPUs and GPUs: Parallelization and RD Analysis

Svetislav Momcilovic, Aleksandar Ilic, Nuno Roma, Leonel Sousa
INESC-ID / IST-TU Lisbon, Rua Alves Redol, 9, 1000-029 Lisboa, Portugal
INESC-ID / IST-TU Lisbon, Tech report, 2013

   author={Svetislav Momcilovic and Aleksandar Ilic and Nuno Roma and Leonel Sousa},

   title={Advanced Video Coding on CPUs and GPUs: Parallelization and RD Analysis},






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Increasing need for high quality video communication and video streaming, and tremendous growth of video content on Internet stimulated development of highly efficient compression methods. H.264/AVC is the newest international video coding standard, which achieves compression gain of about 50% comparing the previous standards, keeping the same quality of reconstructed video [1]. However, such compression efficiency is payed by dramatic increase of the computational demands, which makes the video coding hard to be achieved in real-time on single-core Cental Processor Units (CPUs). The commodity computers of the latest generation, equipped with both multi-core CPUs and many-core Graphical Processing Units (GPUs), are able to achieve high performance in various signal processing algorithms. GPUs’ architectures usually consist of hundreds of cores, especially adapted to exploit fine-grained parallelism. As such, GPUs have proven to be highly efficient in exploiting data-parallel parallelism and have been frequently applied to implement complex signal processing applications. On multi-core CPUs, on the other hand, data-parallelism can be exploited either at a lower level, by using vector instructions, or at a higher level, by concurrently running multiple threads on different cores. The simultaneous exploitation of all these different parallelization models involving both the CPUs and the GPUs conducts to complex but rather promising challenges that are widely attractive and worth to be exploited by the most computational demanding applications. However, even though these devices are able to run asynchronously, efficient parallelization models are needed to exploit such computational power of concurrently running devices. These models must guarantee respecting of data dependencies in the parallelized algorithm, aiming in the same time to achieve load balanced execution on processing devices.
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