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The Hierarchical Memory Machine Model for GPUs

Koji Nakano
Department of Information Engineering, Hiroshima University
International Parallel and Distributed Processing Symposium Workshops, 2013

@article{nakano2013hierarchical,

   title={The Hierarchical Memory Machine Model for GPUs},

   author={Nakano, Koji},

   year={2013}

}

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The Discrete Memory Machine (DMM) and the Unified Memory Machine (UMM) are theoretical parallel computing models that capture the essence of the shared memory access and the global memory access of GPUs. The main contribution of this paper is to introduce the Hierarchical Memory Machine (HMM), which consists of multiple DMMs and a single UMM. The HMM is a more practical parallel computing model which reflects the architecture of current GPUs. We present several fundamental algorithms on the HMM. First, we show that the sum of numbers can be computed in O(n/w+nl/p+l+logn) time units using p threads on the HMM with width w and latency l, and prove that this computing time is optimal. We also show that the direct convolution of m and (m+n-1) numbers can be done in O(n/w+mn/(dw)+nl/p+l+logm) time units using p threads on the HMM with d DMMs, width, and latency l. Finally, we prove that our implementation of the direct convolution is time optimal.
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