Best Practice Guide – Intel Xeon Phi

Michaela Barth, Mikko Byckling, Nevena Ilieva, Sami Saarinen, Michael Schliephake, Volker Weinberg
KTH Sweden
PRACE Best Practice Guides, 2013

   title={Best Practice Guide Intel Xeon Phi v0.},

   author={Barth, Michaela and Sweden, KTH and Byckling, Mikko and Finland, CSC and Ilieva, Nevena and Bulgaria, NCSA and Saarinen, Sami and Schliephake, Michael and Weinberg, Volker and Germany, LRZ},



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This best practice guide provides information about Intel’s MIC architecture and programming models for the Intel Xeon Phi coprocessor in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications. This is a very preliminary draft of the Best Practice Guide which is still under development. Several informations from publicly available Intel documents and especially recent webinars [9] have been incorporated into the current draft. It further contains contributions from CSC, KTH, LRZ, and NCSA. The final version will include more experience gained within PRACE with the Intel Xeon Phi coprocessor and will be available in the end of December 2013. Recently the first book about programming the Intel Xeon Phi coprocessor [1] has been published. We also recommend a book about structured parallel programming [2]. Useful online documentation about the Intel Xeon Phi coprocessor can be found in Intel’s developer zone for Xeon Phi Programming [4] and the Intel Many Integrated Core Architecture User Forum [5]. To get things going quickly have a look on the Intel Xeon Phi Coprocessor Developer’s Quick Start Guide [13] and also on the paper [20].
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