high performance computing on graphics processing units: hgpu.org

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Fast circuit simulation on graphics processing units

Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry

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Tags: Computer science, CUDA, Electronic design automation, nVidia, nVidia GeForce 8800 GTS

July 14, 2011 by hgpu

Fast variational static IR-drop analysis on the graphical processing unit

R.O. Topaloglu

Tags: Computer science, Electronic design automation

June 30, 2011 by hgpu

High Performance Processor Development for Consumer Electronics Game Processor Perspective

J.D. Brown

Tags: Computer science, Electronic design automation

June 28, 2011 by hgpu

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu

Tags: Computer science, Electronic design automation, Hardware Architecture, nVidia

June 24, 2011 by hgpu

Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming

Won Ha Choi, Xun Liu

Tags: Algorithms, CAD, Computer science, Electronic design automation

June 23, 2011 by hgpu

GCS: High-Performance Gate-Level Simulation with GP-GPUs

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco

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Tags: CAD, Computer science, CUDA, Electronic design automation, nVidia, nVidia GeForce 8800 GT

June 23, 2011 by hgpu

GPU-accelerated fault simulation and its new applications

Huawei Li, Dawen Xu, Kwang-Ting Cheng

Tags: Computer science, Electronic design automation, Fault simulation

June 23, 2011 by hgpu

High performance gate-level simulation with GP-GPU computing

Valeria Bertacco, Debapriya Chatterjee

Tags: CAD, Computer science, Electronic design automation

June 22, 2011 by hgpu

Parallel cross-layer optimization of high-level synthesis and physical design

James Williamson, Yinghai Lu, Li Shang, Hai Zhou, Xuan Zeng

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Tags: CAD, Computer science, CUDA, Electronic design automation, nVidia, Tesla C1060

June 15, 2011 by hgpu

A Reconfigurable Processor for Phylogenetic Inference

Pei Liu, Ahmed Hemani, Kolin Paul

Tags: Computer science, Electronic design automation, FPGA, Performance

June 15, 2011 by hgpu

Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis

Jiying Xue, Xiaomeng Jiao, Yangdong Deng, Hao Qian, Dajie Zeng, Guoyu Li, Zhiping Yu

Tags: CUDA, Electronic design automation, FEM, Finite element method, nVidia

June 2, 2011 by hgpu

Distributed time, conservative parallel logic simulation on GPUs

Bo Wang, Yuhao Zhu, Yangdong Deng

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Tags: Computer science, CUDA, Electronic design automation, Hardware Architecture, nVidia, nVidia GeForce GTX 280, Performance

May 31, 2011 by hgpu

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

Optical flow algorithms for SYCL

SYCL in the edge: performance and energy evaluation for heterogeneous acceleration

OpenMP5-Offload-OpenMC-Intel-PVC

Distributed OpenMP Offloading of OpenMC on Intel GPU MAX Accelerators

See all packages

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high performance computing on graphics processing units: hgpu.org

Fast circuit simulation on graphics processing units

Fast variational static IR-drop analysis on the graphical processing unit

High Performance Processor Development for Consumer Electronics Game Processor Perspective

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips

Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming

GCS: High-Performance Gate-Level Simulation with GP-GPUs

GPU-accelerated fault simulation and its new applications

High performance gate-level simulation with GP-GPU computing

Parallel cross-layer optimization of high-level synthesis and physical design

A Reconfigurable Processor for Phylogenetic Inference

Massively Parallel Finite Element Simulator for Full-Chip STI Stress Analysis

Distributed time, conservative parallel logic simulation on GPUs

Recent source codes

QArray

Celerity: High-level C++ for Accelerator Clusters

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

Optical flow algorithms for SYCL

OpenMP5-Offload-OpenMC-Intel-PVC

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