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Lawrence Tan
This thesis analyses the energy efficiency of a low-power CPU-GPU hybrid architecture. We evaluate the NVIDIA Ion architecture, which couples an Intel Atom low power processor with an integrated GPU that has an order of magnitude fewer processors compared to traditional discrete GPUs. We attempt to create a system that balances computation and I/O capabilities […]
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Chung Hwan Kim, Srikanth Manikarnike, Vaibhav Sharma, Eric Eide, Robert Ricci
Binary translation is the emulation of one instruction set by another through translation of code. In binary translation sequences of instructions are translated from the source to the target instruction set. Dynamic binary translation (DBT) looks at a short sequence of code – typically on the order of a single basic block – then translate […]
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Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas
Power dissipation and energy consumption are becoming increasingly important architectural design constraints in different types of computers, from embedded systems to largescale supercomputers. To continue the scaling of performance, it is essential that we build parallel processor chips that make the best use of exponentially increasing numbers of transistors within the power and energy budgets. […]
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Abhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar
Embedded learning applications in automobiles, surveillance, robotics, and defense are computationally intensive, and process large amounts of real-time data. Systems for such workloads have to balance stringent performance constraints within limited power budgets. High performance computer processing units (CPUs) and graphics processing units (GPUs) cannot be used in an embedded platform due to power issues. […]
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Constantin Timm, Frank Weichert, Peter Marwedel, Heinrich Muller
In this paper, novel objectives for the design space exploration of GPGPU applications are presented. The design space exploration takes the combination of energy efficiency and realtime requirements into account. This is completely different to the commonest high performance computing objective, which is to accelerate an application as much as possible. As a proof-of-concept, a […]
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David Rodenas, Francesc Serratosa, Albert Sole-Ribalta
This paper presents a new parallel algorithm to compute multiple graph-matching based on the Graduated Assignment. The aim of developing this parallel algorithm is to perform multiple graph matching in a current desktop computer, but, instead of executing the code in the generic processor, we execute a parallel code in the graphic processor unit. Our […]
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Geoffrey Blake, Ronald G. Dreslinski, Trevor Mudge, Krisztian Flautner
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing cores on a single chip each generation. The implicit expectation is that software developers will write their applications with concurrency in mind to take advantage of this sudden change […]
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