Porting FEASTFLOW to the Intel Xeon Phi: Lessons Learned
University of Patras, Greece
PRACE, 2014
@article{venetis2014porting,
title={Porting FEASTFLOW to the Intel Xeon Phi: Lessons Learned},
author={Venetis, Ioannis E. and Goumas, Georgios and Geveler, Markus and Ribbrock, Dirk},
year={2014}
}
In this paper we report our experiences in porting the FEASTFLOW software infrastructure to the Intel Xeon Phi coprocessor. Our efforts involved both the evaluation of programming models including OpenCL, POSIX threads and OpenMP and typical optimization strategies like parallelization and vectorization. Since the straightforward porting process of the already existing OpenCL version of the code encountered performance problems that require further analysis, we focused our efforts on the implementation and optimization of two core building block kernels for FEASTFLOW: an axpy vector operation and a sparse matrix-vector multiplication (spmv). Our experimental results on these building blocks indicate the Xeon Phi can serve as a promising accelerator for our software infrastructure.
February 14, 2014 by hgpu
