Multicore architecture and cache optimization techniques for solving graph problems
Department of Computer Science, California State University Dominguez Hills, Carson, CA, USA
arXiv:1807.03383 [cs.DC], (9 Jul 2018)
@article{tzul2018multicore,
title={Multicore architecture and cache optimization techniques for solving graph problems},
author={Tzul, Alvaro},
year={2018},
month={jul},
archivePrefix={"arXiv"},
primaryClass={cs.DC}
}
With the advent of era of Big Data and Internet of Things, there has been an exponential increase in the availability of large data sets. These data sets require in-depth analysis that provides intelligence for improvements in methods for academia and industry. Majority of the data sets are represented and available in the form of graphs. Therefore, the problem at hand is to address solving graph problems. Since the data sets are large, the time it takes to analyze the data is significant. Hence, in this paper, we explore techniques that can exploit existing multicore architecture to address the issue. Currently, most Central Processing Units have incorporated multicore design; in addition, co-processors such as Graphics Processing Units have large number of cores that can used to gain significant speedup. Therefore, in this paper techniques to exploit the advantages of multicore architecture is studied.
July 15, 2018 by hgpu
