An FPGA-based Torus Communication Network
INFN and University of Ferrara, Via Saragat 1, I-44100 Ferrara, Italy
arXiv:1102.2346 [hep-lat] (11 Feb 2011)
@article{2011arXiv1102.2346P,
author={Pivanti}, M. and {Fabio Schifano}, S. and {Simma}, H.},
title={“{An FPGA-based Torus Communication Network}”},
journal={ArXiv e-prints},
archivePrefix={“arXiv”},
eprint={1102.2346},
primaryClass={“hep-lat”},
keywords={High Energy Physics – Lattice, Computer Science – Distributed, Parallel, and Cluster Computing},
year={2011},
month={feb},
adsurl={http://adsabs.harvard.edu/abs/2011arXiv1102.2346P},
adsnote={Provided by the SAO/NASA Astrophysics Data System}
}
We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results.
February 14, 2011 by hgpu
