Accelerating Power Flow studies on Graphics Processing Unit
Department of Electrical Engineering, Indian Institute of Technology Roorkee, India
Annual IEEE India Conference (INDICON), 2010 (December 2010), pp. 1-5
@inproceedings{citeulike:8826960,
author={Singh, Jaideep and Aruni, Ipseeta},
citeulike-article-id={8826960},
citeulike-linkout-0={http://dx.doi.org/10.1109/INDCON.2010.5712651},
citeulike-linkout-1={http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5712651},
doi={10.1109/INDCON.2010.5712651},
keywords={gpu, power_flow},
location={Kolkata, India},
month={dec},
pages={1–5},
posted-at={2011-02-16 11:42:35},
priority={5},
title={Accelerating Power Flow studies on Graphics Processing Unit},
url={http://dx.doi.org/10.1109/INDCON.2010.5712651},
year={2010}
}
This paper presents the design of Power Flow algorithm that has enhanced performance on the Graphics Processing Unit (GPU) using Compute Unified Device Architecture (CUDA). This work investigates the performance of optimized CPU versions of Newton-Raphson (Polar form) and Gauss-Jacobi power flow algorithms, highlights the approach used to reduce the computation time by performing these studies on massively parallel GPU cores. Simulations results demonstrate the significant acceleration of the GPU version compared to its CPU variant, thus reducing processing time making them suitable for real-time online dispatching purposes.
February 18, 2011 by hgpu
