Energy-saving techniques for low-power graphics processing unit
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
International SoC Design Conference, 2008. ISOCC ’08
@inproceedings{chang2008energy,
title={Energy-saving techniques for low-power graphics processing unit},
author={Chang, C.M. and Chien, S.Y. and Tsao, Y.M. and Sun, C.H. and Lok, K.H. and Cheng, Y.J.},
booktitle={SoC Design Conference, 2008. ISOCC’08. International},
volume={1},
pages={I–242},
organization={IEEE},
year={2008}
}
This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter/intra adaptive mutli-threading scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for circuit level power reduction, power-aware frequency scaling is proposed to further reduce the power consumption.
July 4, 2011 by hgpu
