A parallel error diffusion implementation on a GPU
University of California, Davis, One Shields Avenue, Davis, CA, USA
IS&T/SPIE Electronic Imaging 2011 / Parallel Processing for Imaging Applications, volume 7872, pages 78720K:1-9, 2011
@inproceedings{Zhang:2011:APE,
author={Yao Zhang and John Ludd Recker and Robert Ulichney and Giordano B. Beretta and Ingeborg Tastl and I-Jong Lin and John D. Owens},
title={A Parallel Error Diffusion Implementation on a {GPU}},
booktitle={Proceedings of SPIE: IS&T/SPIE Electronic Imaging 2011 / Parallel Processing for Imaging Applications},
year={2011,volume=7872,month=jan,pages={78720K:1–9},url={http://www.idav.ucdavis.edu/publications/print_pub?pub_id=1049},doi={10.1117/12.872616},ucdcite={a58}
}
In this paper, we investigate the suitability of the GPU for a parallel implementation of the pinwheel error diffusion. We demonstrate a high-performance GPU implementation by efficiently parallelizing and unrolling the image processing algorithm. Our GPU implementation achieves a 10 – 30x speedup over a two-threaded CPU error diffusion implementation with comparable image quality. We have conducted experiments to study the performance and quality tradeoffs for differences in image block sizes. We also present a performance analysis at assembly level to understand the performance bottlenecks.
October 5, 2011 by hgpu
