A High Performance Parallel FDTD Method Enhanced By Using SSE Instruction Set
Oriental Institute of Technology, Taipei, Taiwan
International Journal of Antennas and Propagation, 2011
@article{chang2011high,
title={A High Performance Parallel FDTD Method Enhanced By Using SSE Instruction Set},
author={Chang, Dau-Chyrh and Yen, Shao-Hsiang and Yang, Xiaoling and Zhang, Lihong and Yu, Wenhua},
year={2011}
}
In this paper, we introduce a hardware acceleration technique for the parallel Finite Difference Time Domain (FDTD) method using the SSE (Streaming SIMD (Single Instruction Multiple Data) Extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has been achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of VALU (Vector Arithmetic Logic Unit) acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.
January 19, 2012 by hgpu
