Towards Building Error Resilient GPGPU Applications
Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, Canada
Workshop on Error Resilient Architectures (WRA), held in conjunction with Micro, 2012
@article{fang2012towards,
title={Towards Building Error Resilient GPGPU Applications},
author={Fang, B. and Wei, J. and Pattabiraman, K. and Ripeanu, M.},
year={2012}
}
GPUs (Graphics Processing Units) have gained wide adoption as accelerators for general purpose computing. They are widely used in error-sensitive applications, i.e. General Purpose GPU (GPGPU) applications However, the reliability implications of using GPUs are unclear. This paper presents a fault injection study to investigate the end-to-end reliability characteristics of GPGPU applications. The investigation showed that 8% to 40% of the faults result in Silent Data Corruption (SDC). To reduce the percentage of SDCs, we propose heuristics to selectively protect specific elements of the application and design error detectors based on heuristics. We evaluate the efficacy of the detectors in reducing SDCs and measure performance overheads of the detectors. Our results show that the heuristics are able to reduce the SDC causing faults by 60% on average, while incurring reasonable performance overheads (35% to 95%).
December 8, 2012 by hgpu
