high performance computing on graphics processing units: hgpu.org

hgpu.org » FPGA

A Simulator for the Cafadis Real Time 3DTV Camera

F. Perez Nava, J. Philip Luke, J. G. Marichal-Hernandez, F. Rosa, J. M. Rodriguez-Ramos

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Tags: Computer science, FPGA, nVidia, nVidia GeForce 7800 GTX, OpenGL, Real-time graphics, Rendering, Stereo vision

July 3, 2011 by hgpu

On the technology roadmap of Free-Viewpoint 3DTV receivers

E. Bondarev, R. Miquel, M. Imbert, S. Zinger, P.H.N. de With

Tags: Computer science, FPGA, Rendering

June 30, 2011 by hgpu

Overview of approaches for accelerating scale invariant feature detection algorithm

Jing Zhang, Hongshi Sang, Xubang Shen

Tags: Computer science, Computer vision, FPGA, SIFT

June 30, 2011 by hgpu

A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement

K. George, C.-I. H. Chen

Tags: FPGA, nVidia, Performance, Signal processing, Tesla C2050

June 30, 2011 by hgpu

Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors

Kostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos

Tags: Algorithms, Computer science, FPGA, Performance, Security

June 22, 2011 by hgpu

Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth

Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto

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Tags: Computer science, FPGA, nVidia, Poster, Tesla C1060

June 21, 2011 by hgpu

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options

Anson H.T. Tse, David B. Thomas, K.H. Tsoi, Wayne Luk

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Tags: CUDA, Finance, FPGA, Monte Carlo simulation, nVidia, Tesla C1060

June 20, 2011 by hgpu

Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU

Matina Lakka, Grigorios Chrysos, Ioannis Papaefstathiou, Apostolos Dollas

Tags: Computer science, FPGA, Information Retrieval, nVidia, Performance

June 16, 2011 by hgpu

A Reconfigurable Processor for Phylogenetic Inference

Pei Liu, Ahmed Hemani, Kolin Paul

Tags: Computer science, Electronic design automation, FPGA, Performance

June 15, 2011 by hgpu

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

Daniel Hefenbrock, Jason Oberg, Nhat Tan Nguyen Thanh, Ryan Kastner, Scott B. Baden

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Tags: Computer science, Computer vision, CUDA, FPGA, GPU cluster, Image recognition, nVidia, nVidia GeForce GTX 285, nVidia GeForce GTX 295

June 15, 2011 by hgpu

FPGA Based High Performance and Scalable Block LU Decomposition Architecture

Manish Kumar Jaiswal, Nitin Chandrachoodan

Tags: Computer science, FPGA, Linear Algebra, Matrix decomposition

June 14, 2011 by hgpu

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan

Tags: Computer science, Computer vision, FPGA, Optimization

June 14, 2011 by hgpu

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

Optical flow algorithms for SYCL

SYCL in the edge: performance and energy evaluation for heterogeneous acceleration

OpenMP5-Offload-OpenMC-Intel-PVC

Distributed OpenMP Offloading of OpenMC on Intel GPU MAX Accelerators

See all packages

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high performance computing on graphics processing units: hgpu.org

A Simulator for the Cafadis Real Time 3DTV Camera

On the technology roadmap of Free-Viewpoint 3DTV receivers

Overview of approaches for accelerating scale invariant feature detection algorithm

A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement

Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core Processors

Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options

Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPU

A Reconfigurable Processor for Phylogenetic Inference

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

FPGA Based High Performance and Scalable Block LU Decomposition Architecture

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Recent source codes

QArray

Celerity: High-level C++ for Accelerator Clusters

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

Optical flow algorithms for SYCL

OpenMP5-Offload-OpenMC-Intel-PVC

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