high performance computing on graphics processing units: hgpu.org

hgpu.org » Hardware Architecture

Supporting x86-64 Address Translation for 100s of GPU Lanes

Jason Power, Mark D. Hill, David A. Wood

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Tags: Benchmarking, Computer science, CUDA, GPGPU-sim, Hardware Architecture, nVidia

January 18, 2014 by hgpu

Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems

Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Pier Stanislao Paolucci, Alessandro Lonardo, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini

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Tags: Computer science, FPGA, GPU cluster, Hardware Architecture, nVidia

November 8, 2013 by hgpu

Exploring Microcontrollers in GPUs

Yusuke Fujii, Takuya Azumi, Nobuhiko Nishio, Shinpei Kato

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Tags: Computer science, CUDA, Hardware Architecture, nVidia, nVidia GeForce GTX 480

August 7, 2013 by hgpu

SIMD Divergence Optimization through Intra-Warp Compaction

Aniruddha S. Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Roy Saharoy, Mani Azimi

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Tags: Computer science, Hardware Architecture, OpenCL, OpenGL, Performance

July 12, 2013 by hgpu

Cost-Effective Soft-Error Protection for SRAM-Based Structures in GPGPUs

Jingweijia Tan, Zhi Li, Xin Fu

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Tags: Computer science, CUDA, Energy-efficient computing, Hardware Architecture, nVidia

June 13, 2013 by hgpu

Performance Evaluation of Sparse Matrix Multiplication Kernels on Intel Xeon Phi

Erik Saule, Kamer Kaya, Umit V. Catalyurek

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Tags: Computer science, CUDA, Hardware Architecture, Intel, Intel Phi, Matrix multiplication, nVidia, Performance, Sparse matrix, Tesla C2050, Tesla K20

February 6, 2013 by hgpu

Survey On The Off-Chip Scheduling of Memory Accesses in the Memory Interface Of GPUs

Luis Angel Garrido Platero

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, Memory, nVidia, Performance

January 31, 2013 by hgpu

GPUDet: A Deterministic GPU Architecture

Hadi Jooybar, Wilson W. L. Fung, Mike O'Connor, Joseph Devietti, Tor M. Aamodt

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Tags: Computer science, GPGPU-sim, Hardware Architecture, nVidia, nVidia GeForce GTX 480

January 29, 2013 by hgpu

Warped Register File: A Power Efficient Register File for GPGPUs

Mohammad Abdel-Majeed, Murali Annavaram

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Tags: Computer science, CUDA, GPGPU-sim, Hardware Architecture, nVidia, Performance

January 28, 2013 by hgpu

GPU Architecture and the Programming Environment

Stanislav Stankovic, Dusan Gajic, Radomir S. Stankovic

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Tags: Computer science, Hardware Architecture, Review

December 10, 2012 by hgpu

Dynamic Warp Resizing in High-Performance SIMT

Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari

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Tags: Computer science, Hardware Architecture, Memory, Performance

August 14, 2012 by hgpu

Investigating Warp Size Impact in GPUs

Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari

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Tags: Computer science, Hardware Architecture

May 23, 2012 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

See all packages

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high performance computing on graphics processing units: hgpu.org

Supporting x86-64 Address Translation for 100s of GPU Lanes

Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems

Exploring Microcontrollers in GPUs

SIMD Divergence Optimization through Intra-Warp Compaction

Cost-Effective Soft-Error Protection for SRAM-Based Structures in GPGPUs

Performance Evaluation of Sparse Matrix Multiplication Kernels on Intel Xeon Phi

Survey On The Off-Chip Scheduling of Memory Accesses in the Memory Interface Of GPUs

GPUDet: A Deterministic GPU Architecture

Warped Register File: A Power Efficient Register File for GPGPUs

GPU Architecture and the Programming Environment

Dynamic Warp Resizing in High-Performance SIMT

Investigating Warp Size Impact in GPUs

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

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