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AnyHLS: High-Level Synthesis with Partial Evaluation

M. Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leissa, Sebastian Hack, Jürgen Teich, Frank Hannig

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Tags: Computer science, FPGA, HLS, Image processing, OpenCL, Package, Programming Languages

August 9, 2020 by hgpu

Synergistic CPU-FPGA Acceleration of Sparse Linear Algebra

Mohammadreza Soltaniyeh, Richard P. Martin, Santosh Nagarakatte

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Tags: Computer science, Factorization, FPGA, HLS, Linear Algebra, Matrix multiplication, OpenCL, Sparse

May 10, 2020 by hgpu

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite

Marius Meyer, Tobias Kenter, Christian Plessl

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Tags: Benchmarking, Computer science, FPGA, HLS, OpenCL, Package

April 26, 2020 by hgpu

Fast Turnaround HLS Debugging using Dependency Analysis and Debug Overlays

Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders,Steven J.E. Wilton

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Tags: Computer science, FPGA, HLS

January 12, 2020 by hgpu

A Highly Parameterizable Framework for Conditional Restricted Boltzmann Machine Based Workloads Accelerated With FPGAs and OpenCL

Zoran Jaksic, Nicola Cadenelli, David Buchaca Prats, Jorda Polo, Josep Lluis Berral Garcia, David Carrera Perez

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Tags: Computer science, FPGA, HLS, Linear Algebra, Matrix multiplication, Neural networks, OpenCL

November 17, 2019 by hgpu

In-memory database acceleration on FPGAs: a survey

Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee

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Tags: Computer science, Databases, FPGA, HLS, OpenCL, survey

November 3, 2019 by hgpu

Performance Debugging Frameworks for FPGA High-Level Synthesis

Young-kyu Choi

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Tags: Benchmarking, Computer science, Design space exploration, FPGA, HLS, Performance, Thesis

October 27, 2019 by hgpu

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Hamid Reza Zohouri, Satoshi Matsuoka

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Tags: Benchmarking, Computer science, FPGA, HLS, Memory, nVidia, OpenCL, Package, Tesla K20, Tesla V100

October 20, 2019 by hgpu

Heterogeneous Resource-Elastic Management for FPGAs: Concepts, Theory and Implementation

Anuj Vaishnav, Dirk Koch, Khoa Dang Pham

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Tags: Computer science, FPGA, Heterogeneous systems, HLS, OpenCL

September 29, 2019 by hgpu

Fast Code Exploration for Pipeline Processing in FPGA Accelerators

Leandro de Souza Rosa

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Tags: Computer science, Design space exploration, FPGA, HLS, Thesis

September 8, 2019 by hgpu

High Performance Computing via High Level Synthesis

Mehdi Roozmeh

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Tags: Computer science, Design space exploration, FPGA, Heterogeneous systems, HLS, Nearest neighbour, nVidia, OpenCL, Package, Signal processing, Thesis

August 18, 2019 by hgpu

FBLAS: Streaming Linear Algebra on FPGA

Tiziano De Matteis, Johannes de Fine Licht, Torsten Hoefler

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Tags: Computer science, FPGA, HLS, Linear Algebra, Package

July 28, 2019 by hgpu

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

SimSYCL: A SYCL Implementation Targeting Development, Debugging, Simulation and Conformance

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

gpu_tracker: Python package for tracking and profiling GPU utilization in both desktop and high-performance computing environments

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

94% on CIFAR-10 in 3.29 Seconds on a Single GPU

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

LOOPer: A Learned Automatic Code Optimizer For Polyhedral Compilers

OpenMC Monte Carlo Code

Performance Portable Monte Carlo Particle Transport on Intel, NVIDIA, and AMD GPUs

Polygeist: C/C++ frontend for MLIR

Retargeting and Respecializing GPU Workloads for Performance Portability

Parallel Gaussian process with kernel approximation in CUDA

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high performance computing on graphics processing units: hgpu.org

AnyHLS: High-Level Synthesis with Partial Evaluation

Synergistic CPU-FPGA Acceleration of Sparse Linear Algebra

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of the HPCChallenge Benchmark Suite

Fast Turnaround HLS Debugging using Dependency Analysis and Debug Overlays

A Highly Parameterizable Framework for Conditional Restricted Boltzmann Machine Based Workloads Accelerated With FPGAs and OpenCL

In-memory database acceleration on FPGAs: a survey

Performance Debugging Frameworks for FPGA High-Level Synthesis

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

Heterogeneous Resource-Elastic Management for FPGAs: Concepts, Theory and Implementation

Fast Code Exploration for Pipeline Processing in FPGA Accelerators

High Performance Computing via High Level Synthesis

FBLAS: Streaming Linear Algebra on FPGA

Recent source codes

SimSYCL: Synchronous, single-threaded, library-only SYCL implementation for debugging and verification

GPU plugin for PySCF

QArray

Celerity: High-level C++ for Accelerator Clusters

gpu_tracker: Context manager and CLI that tracks the computational-resource-usage of a code block or shell command, particularly the GPU usage

CIFAR-10 Airbench: 94% on CIFAR-10 in 3.29 second

LOOPer: a polyhedral compiler for expressing fast and portable data parallel algorithms

OpenMC Monte Carlo Code

Polygeist: C/C++ frontend for MLIR

Parallel Gaussian process with kernel approximation in CUDA

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