{"id":10329,"date":"2013-08-19T23:01:21","date_gmt":"2013-08-19T20:01:21","guid":{"rendered":"http:\/\/hgpu.org\/?p=10329"},"modified":"2013-08-20T18:32:52","modified_gmt":"2013-08-20T15:32:52","slug":"a-domain-specific-language-and-compiler-for-stencil-computations-on-short-vector-simd-and-gpu-architectures","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=10329","title":{"rendered":"A Domain-Specific Language and Compiler for Stencil Computations on Short-Vector SIMD and GPU Architectures"},"content":{"rendered":"<p>Stencil computations are an integral part of applications in a number of scientific computing domains, such as image processing and partial differential equations. We describe a domain-specific language for regular stencil computations, that allows specification of the computations in a concise manner. We describe a multi-target compiler for this DSL, that generates optimized code for multi-core processors with short-vector SIMD engines, as well as GPUs. The hardware differences between these two types of architecture prompt different optimization strategies for the compiler. A data layout transformation along with split tiling is used for multi-core CPUs, while overlapped tiling is used for GPUs. We evaluate our domain-specific compiler for a number of benchmarks on CPU and GPU platforms.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Stencil computations are an integral part of applications in a number of scientific computing domains, such as image processing and partial differential equations. We describe a domain-specific language for regular stencil computations, that allows specification of the computations in a concise manner. We describe a multi-target compiler for this DSL, that generates optimized code for [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,89,3],"tags":[1782,14,95,20,974],"class_list":["post-10329","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-nvidia-cuda","category-paper","tag-computer-science","tag-cuda","tag-high-level-languages","tag-nvidia","tag-nvidia-geforce-gtx-580"],"views":2364,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/10329","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=10329"}],"version-history":[{"count":1,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/10329\/revisions"}],"predecessor-version":[{"id":10349,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/10329\/revisions\/10349"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=10329"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=10329"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=10329"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}