{"id":11558,"date":"2014-03-07T23:57:18","date_gmt":"2014-03-07T21:57:18","guid":{"rendered":"http:\/\/hgpu.org\/?p=11558"},"modified":"2014-03-07T23:57:18","modified_gmt":"2014-03-07T21:57:18","slug":"converting-data-to-task-parallelism-by-rewrites","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=11558","title":{"rendered":"Converting Data to Task-Parallelism by Rewrites"},"content":{"rendered":"<p>High-level domain-specific-languages for array processing on the GPU are increasingly common, but to date they run only on a single GPU. We argue that languages will need to target multiple devices, even simultaneous combinations of GPU\/GPU and CPU\/GPU. Increased flexibility may be key to making these languages more easily deployable and thus widespread. To this end, we present a compositional translation that fissions data-parallel programs in the Accelerate language, allowing subsequent compiler stages to map computations on multiple devices via different code-generation backends. As a result, Accelerate becomes the first EDSL to exercise the CPU and GPU with each data-parallel kernel. Further, because Accelerate code is written at a level of abstraction that does not require per-platform tuning, the same source can run efficiently on and across different devices.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>High-level domain-specific-languages for array processing on the GPU are increasingly common, but to date they run only on a single GPU. We argue that languages will need to target multiple devices, even simultaneous combinations of GPU\/GPU and CPU\/GPU. Increased flexibility may be key to making these languages more easily deployable and thus widespread. To this [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,89,3],"tags":[1782,14,1353,20,176,854,1226],"class_list":["post-11558","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-nvidia-cuda","category-paper","tag-computer-science","tag-cuda","tag-haskell","tag-nvidia","tag-package","tag-task-scheduling","tag-tesla-c2075"],"views":3266,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/11558","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=11558"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/11558\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=11558"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=11558"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=11558"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}