Hardware acceleration is considered a powerful tool in parallel-computing, able to overcome the limitations imposed by sequential execution of software applications and, at the same time, provide energy-efficient alternatives to other parallel computing platforms such as GPUs. However, the increasing application complexity makes it unaffordable to map algorithms directly into HDL. Hence, High-Level Synthesis tools can be used to leverage the design of hardware accelerators from high-level programming languages such as C\/C++ or OpenCL. In this paper, the use of High-Level Synthesis tools to generate hardware accelerators for applications with significant data-level parallelism is evaluated. Multiple copies of the same accelerator are used to analyze performance scalability in two different scenarios: high-performance embedded computing, and small-scale datacenter. In the former, Vivado HLS is used to generate accelerators from C and OpenCL code, which are then compared to several software-based multicore alternatives. In the latter, accelerators are seamlessly integrated using SDAccel, and the OpenCL-based description is also used to establish comparisons with other parallel computing platforms (GPUs). Experimental tests show promising results in the high-performance embedded computing scenario, where hardware-based processing outperforms its software-based counterparts. However, the results obtained in the small-scale datacenter scenario show that FPGA-based acceleration using OpenCL is currently no match for high-end GPU devices in certain applications.<\/p>\n","protected":false},"excerpt":{"rendered":"
Hardware acceleration is considered a powerful tool in parallel-computing, able to overcome the limitations imposed by sequential execution of software applications and, at the same time, provide energy-efficient alternatives to other parallel computing platforms such as GPUs. However, the increasing application complexity makes it unaffordable to map algorithms directly into HDL. Hence, High-Level Synthesis tools […]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,90,3],"tags":[1238,1782,377,20,1767,1793],"class_list":["post-18002","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-opencl","category-paper","tag-arm","tag-computer-science","tag-fpga","tag-nvidia","tag-nvidia-geforce-gtx-titan-x","tag-opencl"],"views":2324,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/18002","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=18002"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/18002\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=18002"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=18002"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=18002"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}