{"id":27501,"date":"2022-11-13T18:46:11","date_gmt":"2022-11-13T16:46:11","guid":{"rendered":"https:\/\/hgpu.org\/?p=27501"},"modified":"2022-11-13T18:46:11","modified_gmt":"2022-11-13T16:46:11","slug":"capturing-the-memory-topology-of-gpus","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=27501","title":{"rendered":"Capturing the Memory Topology of GPUs"},"content":{"rendered":"<p>Optimizing program code is an essential process for High-Performance Computing and in general. Due to a trend in the last years of employing graphics cards as accelerators for systems and due to a universal gain of the importance of GPUs, optimizing GPU code is crucial in order to achieve the best possible performance of a GPU program. The optimization process works best with fundamental background knowledge about the GPU(s) and their structure on which the program will be executed. However, a lot of the relevant information especially regarding the overall memory structures is not or only vaguely documented. For this purpose, this thesis presents the design and implementation of a tool to capture the memory topology of GPUs. This work only considers the GPUs of Nvidia whereas AMD or other manufacturers are not covered.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Optimizing program code is an essential process for High-Performance Computing and in general. Due to a trend in the last years of employing graphics cards as accelerators for systems and due to a universal gain of the importance of GPUs, optimizing GPU code is crucial in order to achieve the best possible performance of a [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,89,3],"tags":[451,1782,14,20,2066,1899,2015,2014,176,67,193,1390,1963,390],"class_list":["post-27501","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-nvidia-cuda","category-paper","tag-benchmarking","tag-computer-science","tag-cuda","tag-nvidia","tag-nvidia-a100","tag-nvidia-geforce-840-m","tag-nvidia-geforce-rtx-2080-ti","tag-nvidia-quadro-p-6000","tag-package","tag-performance","tag-ptx","tag-tesla-k20","tag-tesla-v100","tag-thesis"],"views":1610,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/27501","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=27501"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/27501\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=27501"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=27501"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=27501"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}