{"id":4413,"date":"2011-06-20T10:41:57","date_gmt":"2011-06-20T10:41:57","guid":{"rendered":"http:\/\/hgpu.org\/?p=4413"},"modified":"2011-06-20T10:41:57","modified_gmt":"2011-06-20T10:41:57","slug":"a-scalable-end-to-end-optimized-real-time-image-based-rendering-framework-on-graphics-hardware","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=4413","title":{"rendered":"A Scalable End-to-End Optimized Real-Time Image-Based Rendering Framework on Graphics Hardware"},"content":{"rendered":"<p>This paper presents the system-level overview of a real-time image- based rendering framework performing multiple intermediate view synthesis, completely on the Graphics Processing Unit (GPU). The software design achieves high-performance, yet maintains flexibility and ease of development through a hierarchical layered architecture. The framework implements the intermediate view synthesis by a chain of consecutive processing modules, as an extension to the Middlebury open software structure, allowing it to benchmark quality and execution time of individual modules for end-to-end system performance optimization. The modules can be flexibly coordinated, enabling scalability to run the multiple view synthesis in real-time on both powerful and weak GPUs.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>This paper presents the system-level overview of a real-time image- based rendering framework performing multiple intermediate view synthesis, completely on the Graphics Processing Unit (GPU). The software design achieves high-performance, yet maintains flexibility and ease of development through a hierarchical layered architecture. The framework implements the intermediate view synthesis by a chain of consecutive processing [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,3],"tags":[1782,20,191,226,1117,119,144],"class_list":["post-4413","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-paper","tag-computer-science","tag-nvidia","tag-nvidia-geforce-7900-gtx","tag-nvidia-geforce-8800-gt","tag-nvidia-quadro-fx-1600-m","tag-presentation","tag-rendering"],"views":2487,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4413","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4413"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4413\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4413"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4413"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4413"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}