{"id":4446,"date":"2011-06-24T09:45:49","date_gmt":"2011-06-24T09:45:49","guid":{"rendered":"http:\/\/hgpu.org\/?p=4446"},"modified":"2011-06-24T09:45:49","modified_gmt":"2011-06-24T09:45:49","slug":"design-and-implementation-of-a-time-division-multiplexing-scan-architecture-using-serializer-and-deserializer-in-gpu-chips","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=4446","title":{"rendered":"Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips"},"content":{"rendered":"<p>We present the design and implementation details of a time-division demultiplexing\/multiplexing based scan architecture using serializer\/deserializer. This is one of the key DFT features implemented on NVIDIA&#8217;s Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer\/deserializer module design, test timing consideration, design rule and test pattern verification. Finally, we show silicon data collected from Fermi GPUs.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>We present the design and implementation details of a time-division demultiplexing\/multiplexing based scan architecture using serializer\/deserializer. This is one of the key DFT features implemented on NVIDIA&#8217;s Fermi family GPU (Graphic Processing Unit) chips. We provide a comprehensive description on the architecture and specifications. We also depict a compact serializer\/deserializer module design, test timing consideration, [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,3],"tags":[1782,534,633,20],"class_list":["post-4446","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-paper","tag-computer-science","tag-electronic-design-automation","tag-hardware-architecture","tag-nvidia"],"views":2355,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4446","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4446"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4446\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4446"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4446"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4446"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}