{"id":4514,"date":"2011-06-30T15:59:54","date_gmt":"2011-06-30T15:59:54","guid":{"rendered":"http:\/\/hgpu.org\/?p=4514"},"modified":"2011-06-30T15:59:54","modified_gmt":"2011-06-30T15:59:54","slug":"on-the-technology-roadmap-of-free-viewpoint-3dtv-receivers","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=4514","title":{"rendered":"On the technology roadmap of Free-Viewpoint 3DTV receivers"},"content":{"rendered":"<p>This paper presents the architecture of an innovative 3DTV receiver system, enabling Free-ViewPoint (FVP) interpolation and rendering functionality. We outline the hardware architecture of the receiver, and specify how the design decisions address the extremely high processing requirements of the system. Based on the experience and quantitative data obtained during the receiver prototyping, we present an architecture roadmap for devices with embedded FVP functionality. We identify three major hardware choices for FVP mapping, namely a dedicated hardware unit, FPGA- and GPU solutions, and discuss pros and cons of each choice.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>This paper presents the architecture of an innovative 3DTV receiver system, enabling Free-ViewPoint (FVP) interpolation and rendering functionality. We outline the hardware architecture of the receiver, and specify how the design decisions address the extremely high processing requirements of the system. Based on the experience and quantitative data obtained during the receiver prototyping, we present [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,3],"tags":[1782,377,144],"class_list":["post-4514","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-paper","tag-computer-science","tag-fpga","tag-rendering"],"views":1889,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4514","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4514"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4514\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4514"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4514"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4514"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}