{"id":4570,"date":"2011-07-04T12:12:22","date_gmt":"2011-07-04T12:12:22","guid":{"rendered":"http:\/\/hgpu.org\/?p=4570"},"modified":"2011-07-04T12:12:22","modified_gmt":"2011-07-04T12:12:22","slug":"energy-saving-techniques-for-low-power-graphics-processing-unit","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=4570","title":{"rendered":"Energy-saving techniques for low-power graphics processing unit"},"content":{"rendered":"<p>This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter\/intra adaptive mutli-threading scheme can increase the performance by increasing hardware utilization, and the proposed configurable memory array architecture can reduce off-chip memory accessing frequency by caching both input data and output results. Furthermore, for graphics applications, a geometry-content-aware technique called early-rejection-after-transformation is proposed to remove redundant operations for invisible triangles. As for circuit level power reduction, power-aware frequency scaling is proposed to further reduce the power consumption.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>This paper presents a graphics processing unit with energy-saving techniques. Several techniques and architectures are proposed to achieve high performance with low power consumption. First of all, low power core pipeline is designed with 2-issue VLIW architecture to reduce power consumption while achieving the processing capability of 400MFLOPS or 800MOPS. In addition, inter\/intra adaptive mutli-threading [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,3],"tags":[1782,344,633],"class_list":["post-4570","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-paper","tag-computer-science","tag-energy-efficient-computing","tag-hardware-architecture"],"views":1705,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4570","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=4570"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/4570\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=4570"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=4570"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=4570"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}