Field programmable gate arrays (FPGAs) have the potential to accelerate scientific computing applications due to their highly parallel architecture. However, for programming these architectures efficiently, hardware description languages (HDL), such as Verilog or VHDL, have to be used. Many application developers are not familiar with these HDL languages, because they traditionally develop their applications using high-level and software related design languages such as C, C++ or Matlab. There exist C-to-FPGA tools [1], such as ImpulseC or CatapultC, which leverage the programming of FPGAs. However, they only support the development of accelerator modules and not the design of the environmental communication infrastructure, such as a PCIconnections or a memory controller. In order to connect the newly developed accelerator with the environment on the reconfigurable hardware platform, intellectual properties (IP) have to be bought or the environmental communication infrastructures have to be developed using HDL. Out of this, results a long and costly development cycle for FPGA-based accelerators, which makes it difficult to compete with other accelerator platforms, such as e.g. the NVIDIA Tesla general purpose graphic processing units (GPGPU). These NVIDIA GPGPUs can be programmed with C-based languages, such CUDA or OpenCL. Therefore the development time for applications running on these architectures is easier and faster than for FPGA-based accelerators.<\/p>\n","protected":false},"excerpt":{"rendered":"
Field programmable gate arrays (FPGAs) have the potential to accelerate scientific computing applications due to their highly parallel architecture. However, for programming these architectures efficiently, hardware description languages (HDL), such as Verilog or VHDL, have to be used. Many application developers are not familiar with these HDL languages, because they traditionally develop their applications using […]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,3],"tags":[1782,377,452,70],"class_list":["post-6196","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-paper","tag-computer-science","tag-fpga","tag-heterogeneous-systems","tag-programming-techniques"],"views":1992,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/6196","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=6196"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/6196\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=6196"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=6196"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=6196"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}