Heterogeneous computers – platforms that make use of multiple specialized devices to achieve high throughput or low energy consumption – are difficult to program. Hardware vendors usually provide compilers from a C dialect to their machines, but complete application rewriting is frequently required to take advantage of them. In this thesis, we propose a new approach to building bridges between regular applications written in C and these dialects. From an analysis of the hardware constraints, we propose original code transformations that can meet those constraints, and we combine them using a completely programmable pass manager that can handle the complex compilation flows required by the code generation process for multiple targets. It makes it possible to build a collection of compiler based on the same infrastructure while targeting different architectures. All the code transformations are done at the source level using the PIPS source-to-source compiler framework. New transformations are detailed using denotational semantics on a simplified language and have been combined to build four different compilers : an OpenMP directive generator, a retargetable multimedia instruction generator for SSE, AVX and Neon, an assembly code generator for an FPGA-based image processor and a CUDA generator.<\/p>\n","protected":false},"excerpt":{"rendered":"
Heterogeneous computers – platforms that make use of multiple specialized devices to achieve high throughput or low energy consumption – are difficult to program. Hardware vendors usually provide compilers from a C dialect to their machines, but complete application rewriting is frequently required to take advantage of them. In this thesis, we propose a new […]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,89,3],"tags":[215,1782,14,377,452,20,1234,390],"class_list":["post-6819","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-nvidia-cuda","category-paper","tag-code-generation","tag-computer-science","tag-cuda","tag-fpga","tag-heterogeneous-systems","tag-nvidia","tag-nvidia-quadro-fx-2700-m","tag-thesis"],"views":2391,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/6819","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=6819"}],"version-history":[{"count":0,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/6819\/revisions"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=6819"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=6819"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=6819"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}