{"id":9404,"date":"2013-05-17T23:15:41","date_gmt":"2013-05-17T20:15:41","guid":{"rendered":"http:\/\/hgpu.org\/?p=9404"},"modified":"2013-06-17T03:05:28","modified_gmt":"2013-06-17T00:05:28","slug":"secrets-from-the-gpu","status":"publish","type":"post","link":"https:\/\/hgpu.org\/?p=9404","title":{"rendered":"Secrets from the GPU"},"content":{"rendered":"<p>Acceleration of cryptographic applications on massively parallel computing platforms, such as Graphics Processing Units (GPUs), becomes a real challenge as their decreasing cost and mass production makes practical implementations attractive. We propose a layered trusted architecture integrating random bits generation and parallelized RSA cryptographic computations on such platforms. The GPU-resident, three-tier, MR architecture consists of a RBG, using the GPU as a deep entropy pool; a bignum modular arithmetic library using the Residue Number System; and GPU APIs for RSA key generation, encryption and decryption. Evaluation results of an experimental OpenCL implementation show a 32-40 GB\/s throughput of random integers, and encryptions with up to 16,128-bit long exponents on a commercial mid-range GPUs. This suggests an ubiquitous solution for autonomous trusted architectures combining low cost and high throughput.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Acceleration of cryptographic applications on massively parallel computing platforms, such as Graphics Processing Units (GPUs), becomes a real challenge as their decreasing cost and mass production makes practical implementations attractive. We propose a layered trusted architecture integrating random bits generation and parallelized RSA cryptographic computations on such platforms. The GPU-resident, three-tier, MR architecture consists of [&hellip;]<\/p>\n","protected":false},"author":351,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":false,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[11,90,3,287],"tags":[1782,289,20,373,1793,1395,1800],"class_list":["post-9404","post","type-post","status-publish","format-standard","hentry","category-computer-science","category-opencl","category-paper","category-security","tag-computer-science","tag-modular-arithmetic","tag-nvidia","tag-nvidia-geforce-gtx-275","tag-opencl","tag-rsa","tag-security"],"views":3027,"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/9404","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/users\/351"}],"replies":[{"embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=9404"}],"version-history":[{"count":1,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/9404\/revisions"}],"predecessor-version":[{"id":9598,"href":"https:\/\/hgpu.org\/index.php?rest_route=\/wp\/v2\/posts\/9404\/revisions\/9598"}],"wp:attachment":[{"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=9404"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=9404"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/hgpu.org\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=9404"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}