Improving Communication Performance and Scalability of Native Applications on Intel Xeon Phi Coprocessor Clusters

Karthikeyan Vaidyanathan, Kiran Pamnany, Dhiraj D. Kalamkar, Alexander Heinecke, Mikhail Smelyanskiy, Jongsoo Park, Daehyun Kim, Aniruddha Shet G, Bharat Kaul, Balint Joo, Pradeep Dubey
Parallel Computing Lab, Intel Corporation, Bangalore, India
IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2014

   title={Improving Communication Performance and Scalability of Native Applications on Intel R Xeon Phi TM Coprocessor Clusters},

   author={Vaidyanathan, Karthikeyan and Pamnany, Kiran and Kalamkar, Dhiraj D and Heinecke, Alexander and Smelyanskiy, Mikhail and Park, Jongsoo and Kim, Daehyun and Shet, Aniruddha and Kaul, Bharat and Jo{‘o}, B{‘a}lint and others},



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Intel Xeon Phi coprocessor-based clusters offer high compute and memory performance for parallel workloads and also support direct network access. Many real world applications are significantly impacted by network characteristics and to maximize the performance of such applications on these clusters, it is particularly important to effectively saturate network bandwidth and/or hide communications latency. We demonstrate how to do so using techniques such as pipelined DMAs for data transfer, dynamic chunk sizing, and better asynchronous progress. We also show a method for, and the impact of avoiding serialization and maximizing parallelism during application communication phases. Additionally, we apply application optimizations focused on balancing computation and communication in order to hide communication latency and improve utilization of cores and of network bandwidth. We demonstrate the impact of our techniques on three well-known and highly optimized HPC kernels running natively on the Intel Xeon Phi coprocessor. For the Wilson-Dslash operator from Lattice QCD, we characterize the improvements from each of our optimizations for communication performance, apply our method for maximizing concurrency during communication phases, and show an overall 48% improvement from our previously best published result. For HPL/LINPACK, we show 68.5% efficiency with 97 TFLOPs on 128 Intel Xeon Phi coprocessors; the first ever reported native HPL efficiency on a coprocessor-based supercomputer. For FFT, we show 10.8 TFLOPs using 1024 Intel Xeon Phi coprocessors on the TACC Stampede cluster; the highest reported performance on any Intel Architecture-based cluster and the first such result to be reported on a coprocessor-based supercomputer.
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