high performance computing on graphics processing units: hgpu.org

==================================================== The Fifth International Workshop on GPU Computing and AI (GCA’20) to be held in conjunction with The Eighth International Symposium on Computing and Networking (CANDAR’20),Naha, Okinawa, Japan, November 24-27, 2020 ==================================================== Special announcement regarding COVID-19 situation– Although we are still working with the possibility of having physical meetings for CANDAR 2020 as planned, the […]

★ 2021 2nd International Conference on Frontiers of Intelligent Manufacturing and Automation (CFIMA 2021) — Ei Compendex & Scopus — Call for paperJanuary 13-15, 2021｜Shenzhen, China ★ Venue: Hilton Garden Inn Shenzhen Bao’an, Shenzhen, ChinaJust off G107, the Hilton Garden Inn Shenzhen Bao’an is inside the Xihuicheng Shopping Plaza in the center of the Bao’an […]

★ 2020 International Conference on Cyber Physical Systems and IoT(CPSIOT 2020) — Ei Compendex & Scopus — Call for papersDecember 14-16, 2020｜Bangkok, Thailand ★ CPSIOT 2020 presents researchers, engineers, and academics with an unprecedented opportunity to associate and interact with some of the foremost experts in the field of Cyber Physical Systems and IoT from […]

★ 2020 International Conference on Wireless Networks and Embedded Systems (ICWNES 2020) — Ei Compendex & Scopus — Call for paperDecember 14-16, 2020｜Bangkok, Thailand ★ Researchers, scientists, engineers and industry professionals will join together this year at ICWNES 2020, where the latest research will be unveiled and groundbreaking research projects will be presented. The field […]

★ 2020 International Joint Conference on Signals, Systems and Computers (CSSC 2020) — Ei Compendex & Scopus — Call for papersDecember 14-16, 2020｜Bangkok, Thailand ★ 2020 International Joint Conference on Signals, Systems and Computers (CSSC 2020) will be held in Bangkok, Thailand. From keynote lectures by internationally recognized academics and leading experts, to a forum […]

With the success of deep learning (DL) methods in diverse application domains, several deep learning software frameworks have been proposed to facilitate the usage of these methods. By knowing the frameworks which are employed in big data analysis, the analysis process will be more efficient in terms of time and accuracy. Thus, benchmarking DL software […]

Matrix-free solvers for finite element method (FEM) avoid assembly of elemental matrices and replace sparse matrix-vector multiplication required in iterative solution method by an element level dense matrix-vector product. In this paper, a novel matrix-free strategy for FEM is proposed which computes element level matrix-vector product by using only the symmetric part of the elemental […]

Scientific workloads have traditionally exploited high levels of sparsity to accelerate computation and reduce memory requirements. While deep neural networks can be made sparse, achieving practical speedups on GPUs is difficult because these applications have relatively moderate levels of sparsity that are not sufficient for existing sparse kernels to outperform their dense counterparts. In this […]

With AMD reinforcing their ambition in the scientific high performance computing ecosystem, we extend the hardware scope of the Ginkgo linear algebra package to feature a HIP backend for AMD GPUs. In this paper, we report and discuss the porting effort from CUDA, the extension of the HIP framework to add missing features such as […]

A commonly occurring computation idiom in neural networks is to perform some pointwise operations on the result of a matrix multiplication. Such a sequence of operations is typically represented as a computation graph in deep learning compilers. When compiling to a GPU target, these computations can be individually mapped to manually tuned implementations provided by […]

To meet the surging demand for high-speed computation in an era of stagnating increase in performance per processor, systems designers resort to aggregating many and even heterogeneous processors into single systems. Automatic parallelization tools relieve application developers of the tedious and error prone task of programming these heterogeneous systems. For these tools, there are two […]

The Boolean satisfiability problem, abbreviated as SAT, is the backbone of many applications in VLSI design automation and verification. Over the years, many SAT solvers, both complete and incomplete, have been developed. Complete solvers are usually based on the DPLL (Davis–Putnam–Logemann–Loveland) algorithm, which is a backtracking algorithm. Industrial strength problems are very large and make […]