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Address Selection for Efficient Barriers on the Intel Xeon Phi

Romain Dolbeau
CAPS entreprise, Rennes, France
CAPS entreprise, 2014

@article{dolbeau2014address,

   title={Address Selection for Efficient Barriers on the Intel Xeon Phi},

   author={Dolbeau, Romain},

   year={2014}

}

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Synchronization primitives are a long-standing issue in parallel programming. Barrier in particular are ubiquitous as common paradigm such as OpenMP makes extensive use of them by ending all parallel sections on a barrier by default. The rising number of simultaneous threads in commodity hardware only exacerbate the problem as for a given amount of computation each thread will take less time to finish before having to wait a longer time for threads to synchronize. This paper focuses on the current Intel Xeon Phi which can distribute work to up to 244 threads on 61 cores, and the new challenges created by its specificities and in particular the ring bus connecting the cores. We will show that inter-core communication speed is highly dependent on the physical address of the variable being communicated, and that this fact has implications when building an efficient barrier. Carefully selecting the physical locations of variables involved in inter-thread communications lead to a 15% improvement in latency for the best barrier on the Xeon Phi.
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