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SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor

Masatoshi Kawai, Takeshi Iwashita, Hiroshi Nakashima
Graduate School of Informatics, Kyoto University, Japan
11th International Meeting High Performance Computing for Computational Science, 2014

@article{kawai2014simd,

   title={SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor},

   author={Kawai, Masatoshi and Iwashita, Takeshi and Nakashima, Hiroshi},

   year={2014}

}

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In this paper, we discuss an efficient implementation of the three-dimensional multigrid Poisson solver on a many-core coprocessor, Intel Xeon Phi. We have used the modified block red-black (mBRB) Gauss-Seidel (GS) smoother to achieve sufficient degree of parallelism and high cache hit ratio. We have vectorized (SIMDized) the GS steps in the smoother by introducing a partially SIMDizing technique based on loop splitting. Our numerical tests demonstrate that our implementation performs 35.5% better than the conventional mBRB-GS smoother implementation on Xeon Phi.
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