14606

OpenCL Based Digital Image Projection Acceleration

Bryan Michael Badalamenti
University of Dayton, Dayton, Ohio
University of Dayton, 2015

@phdthesis{badalamenti2015opencl,

   title={OpenCL Based Digital Image Projection Acceleration},

   author={Badalamenti, Bryan Michael},

   year={2015},

   school={University of Dayton}

}

Download Download (PDF)   View View   Source Source   

1687

views

In this thesis, several implementations of an image back projection algorithm using Open Computing Language (OpenCL) for different types of processors are developed. Image back projection is a method to take aerial imagery and create a map-like image that contains real-world dimensions and to remove the perspective angle from the camera. The processors that ran the back projection algorithm include a Central Processing Unit (CPU), a Many Integrated Core (MIC), two Graphic Processing Units (GPUs), and two Field-Programmable Gate Array (FPGA) devices all have different architectures are require different programming styles. OpenCL is a new programming standard that provides a common programming language between the different types of devices using a widely used programming environment. OpenCL follows the C99 Standard and provides support for devices with parallel computing capabilities to help create an optimized solution. Different versions of the back projection algorithm are presented here to examine the flexibility of the OpenCL standard and to create the most optimal solution among the different devices. Timing measurements are compiled for each version of the algorithm for each device and compared against one another and a C++ single threaded host CPU implementation used as a baseline. The fastest implementation for each device is then compared in terms of execution time, throughput, and maximum total dissipated energy (TDE). The presented OpenCL back projection solution provides a 90 times speedup (62.2 ms) on the CPU when compared to the baseline implementation (5680.7 ms) of the algorithm. The throughput for this CPU implementation is 1302.25 megabytes per second (MB/s) and the maximum TDE is 7.2 J per frame.
No votes yet.
Please wait...

* * *

* * *

HGPU group © 2010-2024 hgpu.org

All rights belong to the respective authors

Contact us: