Evaluating 3-D Stencil codes on Intel Xeon Phi: Limitations and Trade-offs
Department of Computer Engineering, University of Murcia, 30100, Murcia
XXVI Edicion de Las Jornadas de Paralelismo, 2015
@article{jose2015evaluating,
title={Evaluating 3-D Stencil codes on Intel Xeon Phi: Limitations and Trade-offs},
author={Jos{‘e}, Mario Hern{‘a}ndez1 Juan M Cebri{‘a}n and Garc{i}a, M Cecilia3 Jos{‘e} M},
year={2015}
}
Accelerators like Intel Xeon Phi aim to fulfill the computational requirements of modern applications. A particular interest to us are those applications that are based on Stencil Computations. Stencils are finite-difference algorithms used in many scientific and engineering applications for solving large-scale and high-dimension partial differential equations. Programmability on massively parallel architectures of such kernels is still a challenge for inexperienced developers. This paper evaluates three stencil-based kernels that are widely applied to simulate heat and acoustic diffusion as well as isotropic seismic wave equation. We focus on key issues that should be considered in order to achieve optimal performance on the Xeon Phi architecture. Among them, we highlight trade-offs between scalability and affinity, blocking and effect of grid shape. Our experimental results yield small performance gains using scatter affinity, showing that the blocking size strongly affects the kernel performance. In addition it reveales that grid shape has minimal impact in performance as long as the best block size is selected.
November 11, 2015 by hgpu
