Optimization and Evaluation of VLPL-S Particle-in-cell Code on Knights Landing
Center for High Performance Computing, Shanghai Jiao Tong University, Shanghai, China
HPC China, 2016
@article{ding2016optimization,
title={Optimization and Evaluation of VLPL-S Particle-in-cell Code on Knights Landing},
author={Ding, Dandi and Wen, Minhua and Zhou, Shan and Chen, Min and Lin, James},
year={2016}
}
VLPL-S code is developed based on the particlein-cell (PIC) algorithm, which is the mainstream algorithm of plasma behavior research. In this paper, we report our early experience on porting and optimizing the VLPL-S particle-in-cell code on the Knights Landing. By applying general optimization methods such as memory access optimization, thread level parallelism and vectorization to the code, we achieved 1.68 times speedup compared to the original code. After optimization, 1.53 times speedup is achieved on Knights Landing 7210P compared with that on a two-socket Xeon E5-2697v4 node. In this work, the performance improvement of different optimization methods on Knights Landing and the Xeon-based node is compared. The results show that most of the commonly used optimization methods are effective for the VLPL-S code on Knights Landing.
November 23, 2016 by hgpu
