Best Practice Guide Intel Xeon Phi v2.0
IICT-BAS, Bulgaria
PRACE, 2017
@article{atanassov2017best,
title={Best Practice Guide Intel Xeon Phi v2.0},
author={Atanassov, Emanouil and Barth, Michaela and Byckling, Mikko and Codreanu, Vali and Ilieva, Nevena and Karasek, Tomas and Rodriguez, Jorge and Saarinen, Sami and Saastad, Ole Widar and Schliephake, Michael and Stachon, Martin and Strassburg, Janko and Weinberg, Volker},
year={2017}
}
This Best Practice Guide provides information about Intel’s Many Integrated Core (MIC) architecture and programming models for the first generation Intel Xeon Phi coprocessor named Knights Corner (KNC) in order to enable programmers to achieve good performance out of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyse and improve the performance of applications. Through the highly parallel architecture and the use of high bandwidth memory, the MIC architecture allows higher performance than traditional CPUs for many types of scientific applications. The guide was created based on the PRACE-3IP Intel Xeon Phi Best Practice Guide. New is the inclusion of information about applications, benchmarks and European Intel Xeon Phi based systems.
February 14, 2017 by hgpu
