17620

Flexible FPGA design for FDTD using OpenCL

Tobias Kenter, Jens Forstner, Christian Plessl
Paderborn Center for Parallel Computing and Department of Computer Science, Paderborn University Warburger Str. 100, 33098 Paderborn, Germany
27th International Conference on Field Programmable Logic and Applications (FPL), 2017

@inproceedings{kenter2017flexible,

   title={Flexible FPGA design for FDTD using OpenCL},

   author={Kenter, Tobias and F{"o}rstner, Jens and Plessl, Christian},

   booktitle={Field Programmable Logic and Applications (FPL), 2017 27th International Conference on},

   pages={1–7},

   year={2017},

   organization={IEEE}

}

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Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.
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