Revolutionary technologies for acceleration of emerging petascale applications

Rupak Biswas, Leonid Oliker and Jeffrey Vetter
NAS Division, NASA Ames Research Center, Moffett Field, CA 94035, USA
Parallel Computing, Volume 35, Issue 3, March 2009, Pages 117-118


   author={Biswas, Rupak and Oliker, Leonid and Vetter, Jeffrey},

   title={Guest editorial: Revolutionary technologies for acceleration of emerging petascale applications},

   journal={Parallel Comput.},











   publisher={Elsevier Science Publishers B. V.},

   address={Amsterdam, The Netherlands, The Netherlands}


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As we enter the era of billion transistor chips, computer architects face significant challenges in effectively harnessing the large amount of computational potential available in modern CMOS technology. Chip designers have been moving away from maximizing single-thread performance via exponential scaling of clock frequencies toward chip multiprocessors (CMPs) in order to better manage trade-offs among performance, energy efficiency, and reliability. Because this design approach is relatively immature, the community is exploring a vast diversity of CMP architectures. System designers and application programmers are confronted with a myriad of architectural features, including multicore, simultaneous multithreading, core heterogeneity, and unconventional memory hierarchies, often combined in novel arrangements. Given the current flux in CMP design, it is unclear which architectural philosophy is best suited for a given class of algorithms. Likewise, this architectural diversity leads to uncertainty on how to reconfigure existing algorithms and tune them to take the maximum advantage of existing and emerging platforms. Understanding the most efficient design and utilization of these increasingly parallel multicore systems is one of the most challenging questions faced by the computing industry in several decades.
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