21648

A Compiler Infrastructure for Embedded Multicore SoCs

Weihua Sheng
Fakultät für Elektrotechnik und Informationstechnik der Rheinisch–Westfälischen Technischen Hochschule Aachen
Rheinisch-Westfälische Technische Hochschule Aachen, 2019

@article{sheng2019compiler,

   title={A Compiler Infrastructure for Embedded Multicore SoCs},

   author={Sheng, M Sc Weihua and Isshiki, Tsuyoshi},

   year={2019}

}

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Compilers play a pivotal role in the software development process for microprocessors, by automatically translating high-level programming languages into machinespecific executable code. For a long time, while processors were scalar, compilers were regarded as a black box among the software community, due to their successful internal encapsulation of machine-specific details. Over a decade ago, major computing processor manufacturers began to compile multiple (simple) cores into a single chip, namely multicores, to retain scaling according to Moore’s law. The embedded computing industry followed suit, introducing multicores years later, amid aggressive marketing campaigns aimed at highlighting the number of processors for product differentiation in consumer electronics. While the transition from scalar (uni)processors to multicores is an evolutionary step in terms of hardware, it has given rise to fundamental changes in software development. The performance "free lunch", having ridden on the growth of faster processors, is over. Compiler technology does not develop and scale for multicore architectures, which contributes considerably to the software crisis in the multicore age. This thesis addresses the challenges associated with developing compilers for multicore SoCs (Systems-On-Chip) software development, focusing on embedded systems, such as wireless terminals and modems. Form follows function. Embedded systems generally address a much narrower application domain than other computing domains do. This requires embedded products that are several degrees more efficient in performance than general-purpose computing products. Therefore, a higher degree of heterogeneity in processors and SoC architecture organization is often perceived as a means of meeting such stringent requirements. Software development for such complex multicore platforms has become a daunting task. Additionally, the life cycles of embedded products are typically much shorter. Consequently, companies’ spending on software engineering has recently skyrocketed. Our approach to tackling the multicore programming challenge is presented herein from a practical perspective. A clean, lightweight C language extension, called CPN (i.e., C for process networks), is designed to capture streaming models that are common in embedded applications. A source-to-source compiler, cpn-cc, was developed as the core component for a multicore compiler infrastructure. Unlike the compilers for scalar processors, cpn-cc requires not only CPN programs as input, but also requires a mapping description that specifies the spatial and temporal mapping of processes to processing elements available in the target multicore platform. The cpn-cc and surrounding software components in the framework are rendered extensible and customizable to various requirements in the multicore design practice. Several real-world multicore platforms, such as TI OMAP 3530 and TI C6678, as well as system-level virtual platforms, have been successfully used as target platforms. Mapping benchmarks onto multicores using this method has achieved good speedups, and software development productivity has also been greatly improved. Moreover, advanced use cases, such as automatic calibration of streaming applications for software mapping exploration and legacy software migration for tablets, have demonstrated the versatility of the multicore compiler infrastructure developed in this work.
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