24496

triSYCL for Xilinx FPGA

Andrew Gozillon, Ronan Keryell, Lin-Ya Yu, Gauthier Harnisch, Paul Keir
School of Computing, Engineering and Physical Sciences
2020 International Conference on High Performance Computing & Simulation (HPCS), 2020

@inproceedings{gozillon2020trisycl,

   title={triSYCL for Xilinx FPGA},

   author={Gozillon, Andrew and Keryell, Ronan and Yu, Lin-Ya and Harnisch, Gauthier and Keir, Paul},

   booktitle={The 2020 International Conference on High Performance Computing & Simulation},

   year={2020},

   organization={IEEE}

}

Khronos SYCL is a C++ based open-source specification that aims to increase the programmability of heterogeneous architectures. Several SYCL implementations exist, with variations both in terms of conformance to the specification; as well as in the range of hardware they target. Intel recently contributed the first open-source feature-complete SYCL implementation to the LLVM compiler project. The triSYCL project is another open-source SYCL implementation which targets Xilinx FPGAs. We describe here initial work to combine components of the triSYCL implementation with Intel’s SYCL implementation, and provide details of the resulting updated compiler infrastructure for targeting the FPGA. We also highlight what is currently possible with the new hybrid triSYCL implementation alongside some interesting extensions for Xilinx FPGAs.
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