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Enabling OpenMP Task Parallelism on Multi-FPGAs

R. Nepomuceno, R. Sterle, G. Valarini, M. Pereira, H. Yviquel, G. Araujo
Institute of Computing, University of Campinas, Brazil
arXiv:2103.10573 [cs.DC], (22 Mar 2021)

@misc{nepomuceno2021enabling,

   title={Enabling OpenMP Task Parallelism on Multi-FPGAs},

   author={R. Nepomuceno and R. Sterle and G. Valarini and M. Pereira and H. Yviquel and G. Araujo},

   year={2021},

   eprint={2103.10573},

   archivePrefix={arXiv},

   primaryClass={cs.DC}

}

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FPGA-based hardware accelerators have received increasing attention mainly due to their ability to accelerate deep pipelined applications, thus resulting in higher computational performance and energy efficiency. Nevertheless, the amount of resources available on even the most powerful FPGA is still not enough to speed up very large modern workloads. To achieve that, FPGAs need to be interconnected in a Multi-FPGA architecture capable of accelerating a single application. However, programming such architecture is a challenging endeavor that still requires additional research. This paper extends the OpenMP task-based computation offloading model to enable a number of FPGAs to work together as a single Multi-FPGA architecture. Experimental results for a set of OpenMP stencil applications running on a Multi-FPGA platform consisting of 6 Xilinx VC709 boards interconnected through fiber-optic links have shown close to linear speedups as the number of FPGAs and IP-cores per FPGA increase.
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