Bringing OpenCL to Commodity RISC-V CPUs

Tine Blaise, Seyong Lee, Jeff Vetter, Hyesoon Kim
Georgia Institute of Technology, Atlanta, Georgia
Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), 2021


   title={Bringing OpenCL to Commodity RISC-V CPUs},

   author={Blaise, Tine and Lee, Seyong and Vetter, Jeff and Kim, Hyesoon},



The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support of the open-source software stack from compiler tools to full-blown operating systems. Parallel computing with today’s Application Programming Interfaces such as OpenCL has proven to be effective at leveraging the parallelism in commodity multi-core processors and programmable parallel accelerators. However, to the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community. Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research. In this work, we extended an Open-source implementation of OpenCL to target RISC-V CPUs. Our work not only cover commodity multi-core RISC-V processors, but also plethora of lowprofile embedded RISC-V CPUs that often do not support atomic instructions or multi-threading.
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