high performance computing on graphics processing units: hgpu.org

With the end of Dennard Scaling and the imminent end of Moore’s Law, the search for new ways to improve performance in computing systems is increasing. Nowadays, the main approach is to use hardware accelerations to offload the application. However, while this is a power-efficient approach, their development process is costly and time-consuming. In this Thesis, we have implemented a hardware accelerator for LBM, what we initially expected to be one of the most accelerator-friendly benchmarks of SPEC CPU 2017. We have implemented it in a Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS), which simplifies the developing process. With our acceleration strategy we have achieved speedups between 1.3× and 1.5× relative the software implementation for realistic data sets. Moreover, we have analyzed HLS and found out that, while it actually simplifies the developing process, this is still not trivial. Developers still need to know and understand the target architecture and guide tool if we want to achieve near-optimal results.