Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs
Shizuoka Institute of Science and Technology, Fukuroi, Shizuoka, JAPAN
arXiv:2306.04087 [cs.DC], (7 Jun 2023)
@misc{kono2023accelerating,
title={Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs},
author={Fumiya Kono and Naohito Nakasato and Maho Nakata},
year={2023},
eprint={2306.04087},
archivePrefix={arXiv},
primaryClass={cs.DC}
}
General Matrix Multiplication (GEMM) is a fundamental operation widely used in scientific computations. Its performance and accuracy significantly impact the performance and accuracy of applications that depend on it. One such application is semidefinite programming (SDP), and it often requires binary128 or higher precision arithmetic to solve problems involving SDP stably. However, only some processors support binary128 arithmetic, which makes SDP solvers generally slow. In this study, we focused on accelerating GEMM with binary128 arithmetic on field-programmable gate arrays (FPGAs) to enable the flexible design of accelerators for the desired computations. Our binary128 GEMM designs on a recent high-performance FPGA achieved approximately 90GFlops, 147x faster than the computation executed on a recent CPU with 20 threads for large matrices. Using our binary128 GEMM design on the FPGA, we successfully accelerated two numerical applications: LU decomposition and SDP problems, for the first time.
June 11, 2023 by hgpu
