AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management

Topi Leppanen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen
Faculty of Information Technology and Communication Sciences, Tampere University, Tampere, Finland
IEEE Nordic Circuits and Systems Conference (NorCAS), 2023


   title={AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management},

   author={Lepp{"a}nen, Topi and Multanen, Joonas and Lepp{"a}nen, Leevi and J{"a}{"a}skel{"a}inen, Pekka},

   booktitle={2023 IEEE Nordic Circuits and Systems Conference (NorCAS)},





OpenCL provides a consistent programming model across CPUs, GPUs, and FPGAs. However, to get reasonable performance out of FPGAs, OpenCL programs created for other platforms need to be modified. These modifications are often vendor-specific, limiting the portability of OpenCL programs between devices from different vendors. In this paper, we propose AFOCL: a cross-vendor portable programming methodology for FPGAs based on standard OpenCL and a database of bitstreams. It is based on the built-in kernel-abstraction introduced in OpenCL v1.2. FPGA reconfiguration is handled automatically by the proposed OpenCL runtime and is invisible to the software programmer. To demonstrate the cross-vendor portability of the method, it is implemented for a PCIe FPGA card from both AMD and Intel. Templates for efficient dataflow-based kernels are created, which can be extended and tailored for each built-in kernel implementation. With a simple evaluation kernel, the runtimes are 85x and 186x faster than an unoptimized OpenCL C kernel implemented with FPGA vendor tooling, AMD and Intel respectively. Against hand-optimized kernel implementations created with vendor tools, the proposed method reaches the same performance as AMD and is only 1.1x slower than Intel, due to limited clock frequency optimization of the template. Thus, the method provides a flexible cross-vendor programming model for FPGAs with competitive performance. The method enables splitting the roles of software developers, who no longer need to concern themselves with FPGA-specific details, and FPGA hardware developers who populate the database. The proposed method is released in open source and integrated into a popular OpenCL implementation PoCL.
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