Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL
Department of Computer Science, Univ. de Valladolid, Spain
arXiv:2409.03391 [cs.DC], (5 Sep 2024)
@misc{decastro2024challengingportabilityparadigmsfpga,
title={Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL},
author={Manuel de Castro and Francisco J. andújar and Roberto R. Osorio and Rocío Carratalá-Sáez and Diego R. Llanos},
year={2024},
eprint={2409.03391},
archivePrefix={arXiv},
primaryClass={cs.DC},
url={https://arxiv.org/abs/2409.03391}
}
As the interest in FPGA-based accelerators for HPC applications increases, new challenges also arise, especially concerning different programming and portability issues. This paper aims to provide a snapshot of the current state of the FPGA tooling and its problems. To do so, we evaluate the performance portability of two frameworks for developing FPGA solutions for HPC (SYCL and OpenCL) when using them to port a highly-parallel application to FPGAs, using both ND-range and single-task type of kernels. The developer’s general recommendation when using FPGAs is to develop single-task kernels for them, as they are commonly regarded as more suited for such hardware. However, we discovered that, when using high-level approaches such as OpenCL and SYCL to program a highly-parallel application with no FPGA-tailored optimizations, ND-range kernels significantly outperform single-task codes. Specifically, while SYCL struggles to produce efficient FPGA implementations of applications described as single-task codes, its performance excels with ND-range kernels, a result that was unexpectedly favorable.
September 22, 2024 by hgpu
